Sunday, April 26, 2009

P55C, Tillamook

 The P55C (or 80503) was developed by Research from Intel and development centre in Ha�fa, Israel. It was sold under the name of Pentium with MX technology (usually just called Pentium MX); although it was based on the P5 core (the 0.35 �m of process was also employed for this series) which it comprised a new whole of 57 instructions �MX� designed to improve the execution on tasks of multi-media, such as the coding and of the numerical data of media of decoding. The new instructions work on new types of data: packed vectors 64-bit of eight integers to 8 bits, of four integers of 16 bits, two integers with 32 bits, or of an integer 64-bit. Execution of P 55 C.A. improved above the versions preliminary by a doubling the hiding-place central processing unit treatment level 1 16 KiB to 32 KiB.

The central processing units of treatment of book of Pentium P55C used �a mobile module� which held the central processing unit of treatment. This module was a chart with the central processing unit of treatment directly attached to him in a smaller special factor of form. The module broken with the mother chart of book and typically a dish of spacer of heat was installed and contact established with the module. Such books frequently employed the tiddlywinks of Intel 430MX, a 430FX device-tiny room. However, with 0.25 mobile Pentium MX of Tillamook of �m (baptized name of a city in Oregon), the module also held the tiddlywinks 430TX with the cache memory of KiB SRAM of system 512.

I limit myself only to one more in order to reduce complains expect more parts legacy. The next one is Pentium pro.

Pentium pro

 Pentium pro is a microprocessor of architecture of the sixth-generation x86 (P6 core) produced by Intel and in the beginning was designed to replace original Pentium in a full extent of the applications, but later, was tiny room to a narrower role like waiter and piece of high office at end. Pentium pro was capable of combine and the configurations of quadruple-processor. It was presented in a factor of form exceptionally large and rectangular of casing 8 in November 1995. Intel since stopped it in favour of the newer lines at end raised of processor of Xeon.

Pentium pro (given the produced code of Intel 80521), was the first generation of the P6 architecture, which would carry Intel in the following decade well. The design would measure of its initial beginning of 150 megahertz, all the manner up to 1.4 gigahertz with Pentium III. of �Tualatin�. Pentium pro had a theoretical execution of 400 MFLOPS. The various features of the core would continue then that in the core derived called �Banias� in Pentium M and the core from Intel (Yonah), that itself would be transformed into the architecture of core (processor of core 2) in 2006 and following. The execution with the code with 32 bits was excellent and well in front of older Pentium then, by 25-35%; however, the pro execution of 16 bits of Pentium was roughly only 20% faster than Pentium to run the code of 16 bits. It was this, with the pro high price of Pentium, due partly of the L2 hiding-place at any speed, which because rather with the reception of tern for the piece among much the enthusiasts at the house of PC, data predominance at the Windows time of 16 bits 3.1x and MS-DOS (Dung from Microsoft on sale).

The pro (P6) core of Pentium comprised a choice of advanced technologies of RISC, although it was not the first central processing unit of x86 treatment with such an approach - before him, the translation x86 intern already used of processor of NexGen Nx586 to his own whole of instruction of industrial property of RISC86 TM. Perhaps the most obvious sign that the things had changed was that the central processing units of treatment �front end� decoded old instructions IA32 according to the microinstructions that the pro core of RISC then treated. The core of Pentium pro comprised several new technologies, including: speculative execution, superpipelining, a L2 hiding-place advanced, retitrant register, broken down execution, and a broader adress bus of bit 36 (usable by PAE). After the microprocessor was released a bug was discovered in the unit of floating decimal point, generally called the �Pentium bug pro and of Pentium II FPU� and by Intel like �erratum of flag�.

The pro the apparent addition of probable Pentium was his hiding-place of the L2 on-package. When, manufacturing technology does not have feasible licence with the L2 hiding-place to be integrated in the core of processor. Intel in the place placed L2 die separately in the package which always allowed him to function at the same frequency of clock as the core of central processing unit of treatment. Moreover, unlike the hiding-place chart-based which divided the bus of principal system with the central processing unit of treatment, the pro seals of Pentium catched his own bus of behind (called independent bus duel by Intel). For this reason, the central processing unit of treatment could indicate of main memory and mask jointly, considerably reducing a traditional neck. The hiding-place was also �non-blocking�, meaning that the processor could at the same time publish more than one request of hiding-place (up to 4), while reducing hiding-place-miss the penalties.

However, this L2 hiding-place much faster came with some complications. All the versions of the piece were expensive, those with more than 256 KiB being particularly thus. The pro arrangement �of hiding-place of on-package� was single. The processor and the hiding-place were on the matrices separated in the same package and connected narrowly in the bus at any speed. The two matrices - which were very large by the standards of the day - had to be stuck together early in the manufacturing process, before the test was possible. This meant that simple and tiny straw in one or the other dies makes him necessary to throw the whole unit, which was one of the reasons of the pro relatively low output of production of Pentium and of the high cost.

No comments:

Post a Comment